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fn6814 rev 0.00 page 1 of 16 december 5, 2008 fn6814 rev 0.00 december 5, 2008 KAD2710C 10-bit, 275/210/170/105 msps a/d converter datasheet the KAD2710C is the industry s lowest power, 10-bit, 275msps, high perfor mance analog-to-digital converter. it is designed with intersils pr oprietary femtocharge? technology on a standard c mos process. the KAD2710C offers high dynamic perf ormance (55.6dbfs snr @ f in = 138mhz) while consuming less than 265mw. features include an over-range indicator and a selectable divide-by-2 input clock divider. the KAD2710C is one member of a pin-compatible family offe ring 8 and 10-b it adcs with sample rates from 105 to 350msps and lvds-compatible or lvcmos outputs (table 1). th is family of products is available in 68-pin rohs-com pliant qfn packages with exposed paddle. performance is specified over the full industrial temperature range (-40c to +85c). features ? on-chip reference ? internal sample and hold ?1.5v p-p differential input voltage ? 600mhz analog input bandwidth ? twos complement or binary output ? over-range indicator ? selectable ? 2 clock input ? lvcmos outputs ? pb-free (rohs compliant) applications ? high-performance data acquisition ? portable oscilloscope ? medical imaging ? cable head ends ? power-amplifier linearization ? radar and satellite an tenna array processing ? broadband communications ? point-to-point microwave systems ? communications test equipment key specs ? snr = 55.6dbfs at f s = 275msps, f in = 138mhz ? sfdr = 68.5dbc at f s = 275msps, f in = 138mhz ? power consumption <265mw at f s = 275msps pin-compatible family lvcmos drivers 1.21v clock generation s/h inp inn 10-bit 275msps adc clk_p clk_n ovss avss avdd2 clkoutp clkoutn d9 C d0 or 2sc ovdd clkdiv + C avdd3 vref vrefsel vcm 10 table 1. pin-compatible products resolution, speed lvds outputs lvcmos outputs 8 bits 350msps kad2708l-35 8 bits 275msps kad2708l-27 kad2708c-27 8 bits 210msps kad2708l-21 kad2708c-21 8 bits 170msps kad2708l-17 kad2708c-17 8 bits 105msps kad2708l-10 kad2708c-10 10 bits 275msps kad2710l-27 KAD2710C-27 10 bits 210msps kad2710l-21 KAD2710C-21 10 bits 170msps kad2710l-17 KAD2710C-17 10 bits 105msps kad2710l-10 KAD2710C-10 n o t r e c o m m e n d e d f o r n e w d e s i g n s n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
KAD2710C fn6814 rev 0.00 page 2 of 16 december 5, 2008 ordering information part number (note) speed (msps) temp. range (c) package (pb-free) pkg. dwg. # KAD2710C-27q68 275 -40 to +85 68 ld qfn l68.10x10b KAD2710C-21q68 210 -40 to +85 68 ld qfn l68.10x10b KAD2710C-17q68 170 -40 to +85 68 ld qfn l68.10x10b KAD2710C-10q68 105 -40 to +85 68 ld qfn l68.10x10b note: these intersil pb-free plas tic packaged products employ sp ecial pb-free material sets, molding compounds/die attach mater ials, and 100% matte tin plate plus anneal (e3 term ination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations). intersil pb-free products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-free requirements of ipc/je dec j std-020.
KAD2710C fn6814 rev 0.00 page 3 of 16 december 5, 2008 table of contents absolute maximum ratings ....................................... .. 4 thermal information............................................ .......... 4 electrical specifications ...................................... ......... 4 digital specifications ......................................... ........... 5 timing diagram ................................................. ............ 6 timing specifications .......................................... ......... 6 thermal impedance.............................................. ......... 6 esd ............................................................ ..................... 6 pin descriptions ............................................... ............. 7 pinout ......................................................... .................... 8 typical performance curve ...................................... .... 9 functional description ......................................... ........ 12 reset .......................................................... ................ 12 voltage reference.............................................. ........ 12 analog input ................................................... ............ 12 clock input ........... ............... .............. ............ ............. 13 jitter......................................................... ................... 13 digital outputs ................................................ ............ 14 equivalent circuits............................................ ............ 14 layout considerations .......................................... ....... 15 split ground and power planes ................................. 15 clock input considerations..................................... .... 15 bypass and filtering ............ ........... ........... ......... ........ 15 lvcmos outputs................................................. ...... 15 unused inputs .................................................. .......... 15 definitions.................................................... .................. 15 package outline drawing ........................................ ..... 16 l68.10x10b ..................................................... ................ 16
KAD2710C fn6814 rev 0.00 page 4 of 16 december 5, 2008 absolute maximum ratings thermal information avdd2 to avss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 2.1v avdd3 to avss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 3.7v ovdd2 to ovss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 2.1v analog inputs to avss. . . . . . . . . . . . . . . . . -0.4v to avdd3 + 0.3v clock inputs to avss. . . . . . . . . . . . . . . . . . -0.4v t o avdd2 + 0.3v logic inputs to avss (vrefsel, clkdiv) -0.4v to avdd3 + 0.3v logic inputs to ovss (rst, 2sc) . . . . . . . . -0.4v to ovdd2 + 0.3v vref to avss . . . . . . . . . . . . . . . . . . . . . . . -0.4v to avdd3 + 0.3v analog output currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma logic output currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma lvds output currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma operating temperature . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. electrical specifications all specifications apply under t he following conditions unless otherwise noted: avdd2 = 1.8v, avdd3 = 3.3v, ovdd = 1.8v, t a = -40c to +85c (typical s pecifications at +25c), f sample = 350msps, 270msps, 210msps, 170msps and 105msps, f in = nyquist at -0.5dbfs. parameter symbol conditions KAD2710C-27 KAD2710C-21 KAD2710C-17 KAD2710C-10 units min typ max min typ max min typ max min typ max dc specifications analog input full-scale analog input range v fs 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 v p-p full scale range temp. drift a vtc full temp 230 210 198 178 ppm/c common-mode output voltage v cm 860 860 860 860 mv power requirements 1.8v analog supply voltage avdd2 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v 3.3v analog supply voltage avdd3 3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45 v 1.8v digital supply voltage ovdd 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1. 81.9 v 1.8v analog supply current i avdd2 44 51 38 42 35 39 29 33 ma 3.3v analog supply current i avdd3 41 45 33 37 28 32 21 24 ma 1.8v digital supply current i ovdd 26 30 25 28 24 27 23 26 ma power dissipation p d 261 294 222 248 199 224 163 185 mw ac specifications maximum conversion rate f s max 275 210 170 105 msps minimum conversion rate f s min 50 50 50 50 msps differential nonlinearity dnl -1.0 0.8 1.5 -1.0 0.8 1.5 -1.0 0.8 1.5 -1 .0 0.8 1.5 lsb integral nonlinearity inl -2.5 1.0 2.0 -2.5 1.0 1.5 -2.5 1.0 1.5 -2.5 1 .0 1.5 lsb signal-to-noise ratio snr f in = 10mhz 55.7 56.4 56.6 56.6 dbfs f in = nyquist 53.5 55.6 53.5 56.2 53.5 56.5 53.5 56.5 dbfs f in = 430mhz 55.2 54.8 54.6 54.5 dbfs signal-to-noise and distortion sinad f in = 10mhz 55.3 56.1 56.3 56.3 dbfs f in = nyquist 52.5 55.2 52.5 56.0 52.5 56.2 52.5 56.2 dbfs f in = 430mhz 54.4 53.7 53.4 53.2 dbfs
KAD2710C fn6814 rev 0.00 page 5 of 16 december 5, 2008 effective number of bits enob f in = 10mhz 8.9 9.0 9.1 9.1 bits f in = nyquist 8.4 8.9 8.4 9.0 8.4 9.0 8.4 9.0 bits f in = 430mhz 8.7 8.6 8.6 8.5 bits spurious-free dynamic range sfdr f in = 10mhz 68.5 70 71 71 dbc f in = nyquist 62 68.5 62 71.1 62 71 62 72 dbc f in = 430mhz 63.8 62.6 60.1 60.9 dbc two-tone sfdr 2tsfdr f in = 133mhz, 135mhz 68 70 70 71 dbc word error rate wer 10 -12 10 -12 10 -12 10 -12 full power bandwidth fpbw 600 600 600 600 mhz electrical specifications all specifications apply under t he following conditions unless otherwise noted: avdd2 = 1.8v, avdd3 = 3.3v, ovdd = 1.8v, t a = -40c to +85c (typical s pecifications at +25c), f sample = 350msps, 270msps, 210msps, 170msps and 105msps, f in = nyquist at -0.5dbfs. (continued) parameter symbol conditions KAD2710C-27 KAD2710C-21 KAD2710C-17 KAD2710C-10 units min typ max min typ max min typ max min typ max digital specifications parameter symbol conditions min typ max units inputs input voltage high (vrefsel) v ih 0.8*avdd3 v input voltage low (vrefsel) v il 0.2*avdd3 v input current high (vrefsel) i ih v in = avdd3 0 10 a input current low (vrefsel) i il v in = avss -90 -65 -30 a input voltage high (clkdiv) v ih 0.8*avdd3 v input voltage low (clkdiv) v il 0.2*avdd3 v input current high (clkdiv) i ih v in = avdd3 100 65 10 a input current low (clkdiv) i il v in = avss 0 -10 a input voltage high (rst,2sc) v ih 0.8*ovdd2 v input voltage low (rst,2sc) v il 0.2*ovdd2 v input current high (rst,2sc) i ih vin = ovdd 0 10 a input current low (rst,2sc) i il vin = ovss -50 -30 -5 a input capacitance c di 3pf clkp, clkn p-p differential input voltage v cdi 0.5 3.6 v p-p clkp, clkn differential input resistance r cdi 10 m ? clkp, clkn common-mode input voltage v cci 0.9 v lvcmos outputs output voltage high v oh 1.8 v output voltage low v ol 0v output rise time t r 1.8 ns output fall time t f 1.4 ns
KAD2710C fn6814 rev 0.00 page 6 of 16 december 5, 2008 esd electrostatic charge accumulates on humans, tools and equipment and may discharge through any metallic package contacts (pins, balls, exposed paddle, etc.) of an integrated circuit. industry-standard protection techniques have been utilized in the design of this product. however, reasonable car e must be taken in the storage a nd handling of esd sensitive products. contact intersil for th e specific esd s ensitivity rat ing of this product. timing diagram figure 1. lvcmos timing diagram inp inn clkp clkn clkout d[9:0] t a t pid t pcd data n-l l sample n data n invalid t ph data n-l+1 timing specifications parameter symbol min typ max units aperture delay t a 1.7 ns rms aperture jitter j a 200 fs input clock to data propagation delay t pid 3.5 5.0 6.5 ns data hold time t ph -300 ps output clock to data propagation delay t pcd 2.8 3.7 ns latency (pipeline delay) l 28 cycles overvoltage recovery t ovr 1cycle thermal impedance parameter symbol typ unit junction to paddle (note 1) ? jp 30 c/w note: 1. paddle soldered to ground plane.
KAD2710C fn6814 rev 0.00 page 7 of 16 december 5, 2008 pin descriptions pin number name function 1, 14, 18, 20 avdd2 1.8v analog supply 2, 7, 10, 19, 21, 24 avss analog supply return 3 vref reference voltage out/in 4 vrefsel reference voltage select (0:int 1:ext) 5 vcm common-mode voltage output 6, 15, 16, 25 avdd3 3.3v analog supply 8, 9 inp, inn analog input positive, negative 11-13, 29-33, 35, 37, 39, 42, 46, 48, 50, 52, 54, 56, 58, 62, 63, 67 dnc do not connect 17 clkdiv clock divide by two (active low) 22, 23 clkn, clkp clock input complement, true 26, 45, 61 ovss output supply return 27, 41, 44, 60 ovdd2 1.8v lvcmos supply 28 rst power on reset (active low) 34 d0 lvcmos bit 0 (lsb) output 36 d1 lvcmos bit 1 output 38 d2 lvcmos bit 2 output 40 d3 lvcmos bit 3 output 43 clkout lvcmos clock output 47 d4 lvcmos bit 4 output 49 d5 lvcmos bit 5 output 51 d6 lvcmos bit 6 output 53 d7 lvcmos bit 7 output 55 d8 lvcmos bit 8 output 57 d9 lvcmos bit 9 (msb) output 59 or over-range 64-66 connect to ovdd2 68 2sc twos complement select (active low) exposed paddle avss analog supply return
KAD2710C fn6814 rev 0.00 page 8 of 16 december 5, 2008 pinout KAD2710C (68 ld qfn) top view 2sc dnc ovdd2 ovdd2 ovdd2 dnc dnc ovss ovdd2 or dnc d9 dnc d8 dnc d7 dnc avdd2 avss avdd2 avss clkn clkp avss avdd3 ovss ovdd2 rst dnc dnc dnc dnc dnc d0 avdd2 avss vref vrefsel vcm avdd3 avss inp inn avss dnc dnc dnc avdd2 avdd3 avdd3 clkdiv KAD2710C top view not to scale d4 dnc ovss ovdd2 clkout dnc ovdd2 d3 dnc d2 dnc d1 dnc d6 dnc d5 dnc 68 qfn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 47 46 45 44 43 42 41 40 39 38 37 36 35 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 figure 2. pin configuration
KAD2710C fn6814 rev 0.00 page 9 of 16 december 5, 2008 typical performance curves avdd2 = ovdd2 = 1.8v, avdd3 = 3.3v, t a = +25c, f sample = 275msps, f in = 137mhz, a in = -0.5dbfs unless noted. figure 3. snr and sfdr vs f in figure 4. hd2 and hd3 vs f in figure 5. snr and sfdr vs a in figure 6. hd2 and hd3 vs a in figure 7. snr and sfdr vs f sample figure 8. hd2 and hd3 vs f sample 50 55 60 65 70 75 80 0 50 100 150 200 250 300 350 400 450 500 550 f in (mhz) snr(dbfs), sfdr(dbc) snr sfdr -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 0 50 100 150 200 250 300 350 400 450 500 550 f in (mhz) hd2, hd3 (dbc) hd 3 hd 2 40 45 50 55 60 65 70 75 -30 -25 -20 -15 -10 -5 0 a in (dbfs) snr(dbfs), sfdr(dbc) snr sfdr -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -30-25-20-15-10 -5 0 a in (dbfs) hd2, hd3 (dbc) hd3 hd2 50 55 60 65 70 75 80 50 100 150 200 250 300 f sa m p l e (f s ) (msps) snr(dbfs), sfdr(dbc) snr sfdr -100 -95 -90 -85 -80 -75 -70 50 100 150 200 250 300 f sa m p l e (f s ) (msps) hd2, hd3(dbc ) hd2 hd 3
KAD2710C fn6814 rev 0.00 page 10 of 16 december 5, 2008 figure 9. power dissipation vs f sample figure 10. differential nonlinearity vs output code figure 11. integral nonlinearity vs output code figure 12. noise h istogram figure 13. output spectrum; f in = 10mhz figure 14. output spectrum; f in = 134mhz typical performance curves avdd2 = ovdd2 = 1.8v, avdd3 = 3.3v, t a = +25c, f sample = 275msps, f in = 137mhz, a in = -0.5dbfs unless noted. (continued) 100 120 140 160 180 200 220 240 260 280 50 100 150 200 250 300 fsample (fs) (msps) power dissipation (pd) (mw) 0 128 256 384 512 640 768 896 1023 -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 co de dnl (lsbs) 0 128 256 384 512 640 768 896 1023 -1 -0.5 0 0.5 1 code inl (lsbs) 0 20 40 60 80 100 120 -120 -100 -80 -60 -40 -20 0 f requency (mhz) amplitude (db) ain = -0.49dbfs s nr = 56.5dbfs s fdr = 70.0dbc s inad = 55.7dbc hd2 = -94.3dbc hd3 = -70.5dbc 0 20 40 60 80 100 120 -120 -100 -80 -60 -40 -20 0 f reque ncy (mhz) amplitude (db) ain = -0.49dbfs snr = 56.5dbf s sfdr = 71.0dbc sinad = 55.7dbc hd 2 = -84.8dbc hd 3 = -71.0dbc
KAD2710C fn6814 rev 0.00 page 11 of 16 december 5, 2008 figure 15. output spectrum; f in = 300mhz figure 16. two-tone spectrum; f in = 69mhz, 70mhz figure 17. two-tone spectrum; f in = 140mhz, 141mhz figure 18. two-tone spectrum; f in = 300mhz, 305mhz figure 19. snr vs temperature figure 20. calibration time vs f s typical performance curves avdd2 = ovdd2 = 1.8v, avdd3 = 3.3v, t a = +25c, f sample = 275msps, f in = 137mhz, a in = -0.5dbfs unless noted. (continued) 0 20 40 60 80 10 0 120 -120 -100 -80 -60 -40 -20 0 f req uency (mhz) amplitude (db) ain = -0.50dbfs snr = 56.0dbfs sfdr = 63.6dbc sinad = 55.1dbc hd2 = -67.8dbc hd3 = - 63.6dbc 0 20 40 60 80 100 120 -120 -100 -80 -60 -40 -20 0 frequency (mhz) relat ive power (db) a i n = - 7 db fs 2tsf dr = 71dbc imd3 = -78dbfs 0 20 40 60 80 10 0 120 -120 -100 -80 -60 -40 -20 0 f requency (mhz) relative power (db) ain = -7dbfs 2ts fdr = 7 4 .7d b c imd3 = -84.5dbfs 0 20 40 60 80 100 120 -120 -100 -80 -60 -40 -20 0 frequency (mhz) relative power (db) ain = -7dbfs 2tsfdr = 63dbc im d 3 = - 7 5d b f s 50 55 60 65 70 75 -40-20 0 20406080 ambient temperature deg.c snr(dbfs), sfdr(dbc) snr sfdr 200 300 400 500 600 700 800 100 125 150 175 200 225 250 275 f sample (f s ) (msps) t cal (ms)
KAD2710C fn6814 rev 0.00 page 12 of 16 december 5, 2008 functional description the kad2710 is a ten bit, 2 75msps a/d converter in a pipelined architecture. the input voltage is captured by a sample and hold circuit and c onverted to a unit of charge. proprietary charge-domain techniques are used to compare the input to a series of reference charges. these comparisons determine the digital code for each input value. the converter pipeline requires 24 sample clo cks to produce a result. digital error correction is also applied, resulting in a total latency of 28 clock cycles. this is evident to the user as a latency between the start of a conversion and th e data being available on the digital outputs. at power-up, a self-calibration is performed to minimize gain and offset errors. the reset pin (rst) is held low internally a t power-up and will remain in that state until the calibration is complete. the clock frequency should remain fixed during this time. calibration accuracy is maintained for the sample rate at which it is performed, and therefore should be repeated if the clock frequency is changed by more than 10%. recalibration can be initiated via the rst pin, o r power cycling, at any time. reset recalibration of the adc can be initiated at any time by drivin g the rst pin low for a minimum of one clo ck cycle. an open- drain driver is recommended. the calibration sequence is ini tiated on the rising edge of rst , as shown in figure 2 1. the over-range output (or) is set high once rst is pulled low, and re mains in that state until calibration is complete. the or output returns to normal operation at that time, so it is important that the analog inpu t be within the converters full-scale range in order to observe the transition. if the input is in an over-range state the or pin w ill stay high and it will not be po ssible to detect the end of the calibration cycle. while rst is low, the output c lock (clkout) stops toggling and is set low. normal operation of the output clock resumes at the next input clock edge (c lkp/clkn) after rst is deasserted. at 275msps the no minal calibration time is ~240ms. voltage reference the vref pin is the reference voltage which sets the full-scale input voltage for the chip. this p in requires a bypass capacito r of 0.1uf at a minimum. the internally generated bandgap reference voltage is provided by an on-chip voltage buffer.buffer can sink or so urce up to 50a externally. an external voltage may be applie d to this pin to provide a more accurate reference than the internally generated bandgap voltage, or to match the full-scale reference for multiple KAD2710C chips.one option in the latter configuration is to use one KAD2710C's inter nally generated reference as the external reference voltage for the other chips in the syste m. additionally, an externally pro vided reference can be changed from the nominal value to adjust the full-scale input voltage within a limited range. to select whether the full-sca le reference is internally generated or externall y provided, the digit al input vrefsel is set low for internal, or high for external.this pin has interna l pull-up.use the internally ge nerated reference vrefsel can be tied directly to avss, and t o use an exter nal reference vrefsel can be left unconnected. analog input the adc core contains a fully di fferential input (inp/inn) to t he sample and hold circuit. the id eal full-scale input voltage is 1.50v, centered at t he vcm voltage of 0.86v as shown in figure 22. best performance is obtained when the analog inputs are driven differentially. the co mmon-mode output voltage, vcm, should be used to properly bias the inputs as shown in figures 23 and 24. an rf transformer will give the best noise and distortion performance for wi deband and/or high intermediate frequency (if) inputs. two different transformer input schemes are shown in fi gures 23 and 24. figure 21. calibration timing clkp clkn clkoutp rst orp calibration begins calibration complete calibration time figure 22. analog input range 1.0 1.8 0.6 0.2 1.4 inp inn vcm 0.86v 0.75v -0.75v v t
KAD2710C fn6814 rev 0.00 page 13 of 16 december 5, 2008 a back-to-back transformer scheme is used to improve common-mode rejection, which keeps the common-mode level of the input matched to v cm . the value of the shunt resistor should be determined based on the desired load impedance. the sample and hold circuit de sign uses a switc hed capacitor input stage, which creates current spikes when the sampling capacitance is reconnected to the input voltage. this creates a disturbance at the input which must settle before the next sampling point. lower source im pedance will result in faster settling and improved perf ormance. therefore a 1:1 transformer and low shunt re sistance are recommended for optimal performance. a differential amplifier can be u sed in applicatio ns that requi re dc coupling. in this configurati on the amplifie r will typically determine the achievable s nr and distortion. a typical differential amplifier circuit is shown in figure 25. clock input the sample clock input circuit is a differential pair (see figu re 29). driving these inputs with a high level (up to 1.8v p-p on each input) sine or square wave w ill provide the lowest jitter performance. the recommended drive circuit i s shown in figure 26. the clock can be driven single-ended, but this will reduce the edge rate and may impact snr performance. use of the clock divider is optional. the KAD2710C's adc requires a clock with 50% duty cycle for optimum performance. if such a clock is not available , one option is to generate twi ce the desired sampling rate and use the KAD2710C's divide-by-2 setting. this frequency divide r uses the ris ing edge of the clock, so 50% clock duty cycle is assured. t able 2 describes the clkdiv connection. clkdiv is internally pulled low, so a pull-up resistor or logic driver must be connected for undivided clock. jitter in a sampled data system, clo ck jitter directly impacts the achievable snr performance. t he theoretical relationship between clock jitter (t j ) and snr is shown in equation 1 and is illustrated in figure 27. where t j is the rms uncertainty i n the sampling instant. figure 23. transformer input for general applications adt1-1wt 0.1f kad2710 vcm 50 o 0.01f analog in adt1-1wt ? ? kad2710 vcm adtl1-12 1nf 1nf analog input figure 24. transmission-line transformer input for high if applications kad2710 vcm 0.1f 0.22f 69.8o 49.9o 100o 100o 69.8o 348o 348o cm 217o 25o 25o analog input figure 25. differential amplifier input ? ? ? ? ? ? ? ? ? ? table 2. clkdiv pin settings clkdiv pin divide ratio avss 2 avdd 1 tc4-1w 1nf avdd2 200o clkp clkn 1ko 1ko 1nf clock input figure 26. recommended clock drive ? ? ? ? f in t j ------------------- - ?? ?? = (eq. 1) tj=100p s tj = 1 0p s tj = 1 p s tj=0.1p s 10 b i ts 12 bits 14 bits 50 55 60 65 70 75 80 85 90 95 10 0 1 10 100 1000 input frequency - mhz snr - d b figure 27. snr vs clock jitter
fn6814 rev 0.00 page 14 of 16 december 5, 2008 KAD2710C intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2008. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. this relationship shows the s nr that would be achieved if clock jitter were the only non -ideal factor. in reality, achievable snr is limited by internal factors such as linearity, aperture jit ter and thermal noise. internal aperture jitter is the uncertainty in the sampling instant shown in figure 1. the internal aperture jitter combines with the input clock jitter in a root-sum-square fashion, since they are not statistically correlated, and thi s determines the total jitter in the system. the total jitter , combined with other noise sources, then determine s the achievable snr. digital outputs data is output on a parallel bus with lvcmos drivers. the output format (binary or twos complement) is selected via the 2sc pin as shown in table 3. table 3. 2sc pin settings 2sc pin mode avss twos complement avdd (or unconnected) binary equivalent circuits figure 28. analog inputs figure 29. clock inputs figure 30. lvcmos outputs avdd3 inp inn avdd3 f1 f1 f2 csamp 0.3pf to charge pipeline 2pf 2pf f2 csamp 0.3pf to charge pipeline ? ? ? ? avdd2 clkp clkn avdd2 avdd2 to clock generation d[9:0] ovdd ovdd data
KAD2710C fn6814 rev 0.00 page 15 of 16 december 5, 2008 layout considerations split ground and power planes data converters operating at high sampling frequencies require extra care in pc board layout. if analog and digital ground planes are separate, analog supply and ground planes should be laid out under signal and clo ck inputs and digital planes under outputs and logic pins. grounds should be joined under the chip. clock input considerations use matched transmission lines to the inputs for the analog input and clock signals. loca te transformers, drivers and terminations as close to the chip as possible. bypass and filtering bulk capacitors should have lo w equivalent series resistance. tantalum is recommended. keep ceramic bypass capacitors very close to devi ce pins. longer tra ces will increase inductance, resulting in dimin ished dynamic performance and accuracy. make sure that connections to ground are direct, and low impedance. lvcmos outputs output traces and connecti ons must be designed for 50 ? characteristic impedance. k eep trace lengths equal, and minimize bends where possible. avoid crossing ground and power-plane breaks with signal traces. unused inputs the rst and 2sc inputs are inte rnally pulled up, and can be left open-circui t if not used. clkdiv is internally pulled low, which divides the input clock by two. vrefsel must be held low for internal r eference, but can be left open for external reference. definitions analog input bandwidth is the analog input frequency at which the spectral output powe r at the fundam ental frequency (as determined by fft analysis ) is reduced by 3db from its full-scale low-frequency value. this is also referred to as ful l power bandwidth. aperture delay or sampling delay is the time r equired after the rise of the clock input for the sampling swit ch to open, at which time the signal is held for conversion. aperture jitter is the rms variation in aperture delay for a set of samples. clock duty cycle is the ratio of t he time the clo ck wave is at logic high to the total time of one clock period. differential non-linearity (dnl) is the deviati on of any code width from an ideal 1 lsb step. effective number of bits (enob) is an alternat e method of specifying signal to noise-and-distortion ratio (sinad). in db, it is calculated as: enob = (sinad - 1.76)/6.02 gain error is the ratio of the differ ence between the voltages that cause the lowest and hi ghest code transitions to the full-scale voltage (less 2 lsb). it is typically expressed in percent. integral non-linearity (inl) is the deviation of each individual code from a line drawn from negative full-scale (1/2 lsb below the first code t ransition) through positi ve full-scale (1/2 lsb above the last code transition). the deviation of any given code from this line is measured from the center of that code. least significan t bit (lsb) is the bit that has the smallest value or weight in a digital wor d. its value in terms of input voltage is v fs /(2 n - 1) where n is the r esolution in bits. missing codes are output codes tha t are skipped and will never appear at the adc output. these codes cannot be reached with any input value. most significant bit (msb) is the bit that has the largest value or weight. pipeline delay is the number of cloc k cycles between the initiation of a conversion and the appearance at the output pin s of the data. power supply rejection ratio (psrr) is the ratio of a change in input voltage nece ssary to correct a change in output code that results fro m a change in power supply voltage. signal to noi se-and-distortion (sinad) is the ratio of the rms signal amplitude to the rm s sum of all other spectral components below one half the clock frequency, including harmonics but excluding dc. signal-to-noise ratio (snr) (without harmonics) is the ratio of the rms signal amplitude to the rms sum of all other spectral components below one-ha lf the sampling frequency, excluding harmonics and dc. snr and sinad are either given in units of dbc (db to carrier) when the power level of the fundamental is used as the reference, or dbfs (db to full scale) when the converters full - scale input power is used as the reference. spurious-free-dyna mic range (sfdr) is the ratio of the rms signal amplitude t o the rms value of the peak spurious spectral component. the peak spurious spectral component may or may not be a harmonic. two-tone sfdr is the ratio of the rms value of the lowest power input tone to the rms value of the peak spurious component, which may or m ay not be an imd product.
KAD2710C fn6814 rev 0.00 page 16 of 16 december 5, 2008 package outline drawing l68.10x10b 68 lead quad flat no-lead plastic package rev 0, 11/08 located within the zone indicated . the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metalli zed terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amsey14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view typical recommended land pattern top view bottom view c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 b 6 pin 1 index area 17 1 34 18 0.10 a mc b 4 a 4x 8.00 68x 0.55 68x 0.25 64x 0.50 10.00 10.00 0.90 max 68x 0.25 68x 0.75 64x 0.50 7.70 sq 9.65 sq 6 pin 1 index area exp. dap 7.70 sq. see detail "x" seating plane 0.08 0.10 c c c 8.00 sq (4x) 0.15 35 51 52 68

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